Complementary metal-oxide-semiconductor (CMOS) integrated circuits are finding increased use in electronic applications, particularly where low power consumption is a desirable characteristic. With regards to their operating voltages, a CMOS integrated circuit can generally be either a low voltage transistor which operates at voltages of no greater than about six volts, or a high voltage transistor whose operating voltage is in excess of about thirty volts. Low voltage transistors are generally used at the logic and intermediate stages of signal processing while, in contrast, high voltage transistors are often used as current drivers and switches, serving at the input and output stages of the integrated circuit.
In that high and low voltage transistors operate in cooperation with each other, it is often desirable to fabricate these devices on the same substrate. However, a distinguishing characteristic of high voltage circuits is that they require a channel region between the source and drain which can withstand a higher induced electric field without experiencing avalanche breakdown, a well known phenomenon in which electron hole pairs are generated by the electric field, producing excessive currents. As a consequence, high and low voltage circuits are generally different in form, as well as having differences in their fabrication processes. Such differences have generally dictated that high and low voltage circuits be formed on separate chips rather than combined on a common substrate.
U.S. Pat. No. 5,047,358 to Kosiak et al., assigned to the assignee of the present invention, teaches a method in which both high and low voltage transistors can be formed on the same substrate. While CMOS integrated circuits of this type perform well, exhibiting large breakdown voltages of 60 volts or more, it would be highly desirable to improve the area efficiency of these devices by decreasing the source-drain channel resistance (RDS.sub.on), particularly in terms of being able to employ both high and low voltage devices in Very Large Scale Integration (VLSI) and UltraLarge Scale Integration (ULSI) CMOS processes.
Lateral Diffused MOSFETs (LDMOS) are a type of high voltage transistors which are well known in the art. These transistors are characterized by desirable attributes such as area efficiency, low channel resistance (i.e., a low RDS.sub.on value) and high voltage breakdown capability which make them highly suitable for current drivers. The high voltage breakdown capability of a LDMOS device, as compared to conventional CMOS logic devices, is due to a resistive drift region in the drain that reduces the impact ionization and peak electric fields.
As illustrated in FIG. 1, a conventional LDMOS device 10 is characterized by an implant 22 of one conductivity-type within a well region 14 of the opposite conductivity-type. In particular, the implant 22 is self-aligned to the source end of the gate electrode 18, necessitating that the gate electrode 18 be formed prior to forming the implant 22. Alignment of the implant 22 with the gate electrode 18 permits accurate placement of the self-aligned implant 22 for purposes of enhancing area efficiency. The self-aligned implant's dopant, illustrated in this case as acceptors, overwhelms the well's dopant, in this case, donors, so as to form the low resistance channel adjacent the gate electrode 18. The doped impurity in the channel increases the concentration of acceptors in the channel, thereby decreasing the depletion width spreading of the source-drain region of the device. As a result, the channel length can be smaller such that the RDS.sub.on value decreases and the current driving capability of the device 10 is increased.
However, because the implant 22 is self-aligned with the gate electrode, the implant 22 must be laterally diffused beneath the gate electrode 18 so as to extend the channel beneath the gate of the transistor 10. To do this, a high temperature drive, typically at a temperature of about 1100.degree. C. or higher, is used to laterally diffuse the self-aligned implant 22.
Though the above operational characteristics of the LDMOS are desirable in terms of enabling the fabrication of an area efficient, high voltage transistor within an integrated circuit, the required high temperature drive is generally incompatible with VLSI and ULSI processes. Particularly, the high temperature drive causes the excessive diffusion of implants in other CMOS circuit devices on the same substrate, thus foreseeably changing the electrical characteristics of the devices and also possibly inducing stresses in smaller devices which may lead to current leakage. Furthermore, because of the high temperature drive required by an LDMOS, typical LDMOS processing with CMOS devices requires multiple levels of polysilicon to define the low voltage CMOS gates, in addition to the polysilicon level that defines the LDMOS gate. Therefore, LDMOS processing is not generally conducive to up-integrating into VLSI and ULSI CMOS processes.
Thus, what is needed is an area efficient, high voltage CMOS device which is also compatible with VLSI and ULSI processes. Such a device would enable the fabrication of CMOS integrated circuits having both high and low voltage transistors on the same substrate. Preferably, such a device would exhibit a large field-induced avalanche breakdown voltage, while also offering low channel resistance so as to result in an area efficient, high voltage switch which can be up-integrated onto logic integrated circuits with VLSI and ULSI processes.